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MEDIA ALERT: ProPlus Design Solutions to Demonstrate Design for Yield Solutions at EDSFair 2012

Transistor-Level Modeling, Design, Variations-Award Products to Be Showcased

SAN JOSE, CA -- (Marketwire) -- 11/08/12 --


WHO: ProPlus Design Solutions, Inc. (www.proplussolutions.com), provider of unique Design for Yield (DFY) solutions that integrate device modeling, parallel SPICE simulation and statistical analysis

WHAT: Will demonstrate NanoYield™, fast and accurate yield prediction and optimization software for memory, logic, analog and digital circuit design, along with its transistor-level statistical modeling and design and variations-aware product portfolio. Products include High Sigma analysis, advanced Monte Carlo analysis and NanoSPICE™ parallel SPICE simulator to accelerate statistical simulation performance.

WHEN: November 14-16, 2012

WHERE: Electronic Design and Solution Fair (EDSFair 2012) in Booth #D-26 at Pacifico Yokohama in Nishi-ku, Yokohama

Dr. Bruce McGaughy, ProPlus Design Solutions' chief technology officer and senior vice president of engineering, will present, "Challenge to Analog/Mixed Signal design optimization by 6 Sigma," Friday, November 16, from 10 to 10:45 a.m. He will give an overview of yield analysis and the technologies and solutions to make it more reliable and realistic.

Details about EDSFair 2012 can be found at: http://www.edsfair.com/e/

About ProPlus Design Solutions

ProPlus Design Solutions, Inc. delivers Electronic Design Automation (EDA) solutions that enhance the link between design and manufacturing. It provides unique Design for Yield (DFY) solutions that integrate device modeling software, a parallel SPICE engine and statistical analysis algorithms. Products include: BSIMProPlus™, a leading device modeling technology platform for nanometer device fabrication, NanoSpice™, a full-chip parallel SPICE simulator with full-chip capacity and SPICE accuracy for transistor-level statistical simulation and analysis, and NanoYield™, a DFY platform to meet performance and yield optimization challenges of advanced memory, analog and digital circuit designs. ProPlus Design Solutions has R&D centers in the San Jose, Calif., Beijing and Jinan, China, and offices in Tokyo, Japan, Hsinchu, Taiwan, and Shanghai, China. More information about ProPlus Design Solutions can be found at www.proplussolution.com.

BSIMProPlus, NanoSpice and NanoYield are registered trademarks of ProPlus Design Solutions. ProPlus Design Solutions acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for ProPlus Design Solutions
(617) 437-1822
Email Contact

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