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JEDEC Releases LPDDR4 Standard for Low Power Memory Devices
|By Business Wire
|August 25, 2014 01:52 PM EDT
Solid State Technology Association, the global leader in standards
development for the microelectronics industry, today announced the
publication of JESD209-4 Low Power Double Data Rate 4 (LPDDR4). Designed
to significantly boost memory speed and efficiency for mobile computing
devices such as smartphones, tablets, and ultra-thin notebooks, LPDDR4
will eventually operate at an I/O rate of 4266 MT/s, twice that of
LPDDR3. The new interface promises to have an enormous impact on the
performance and capabilities of next-generation portable electronics.
“LPDDR4 represents a dramatic performance increase,” said Mian Quddus,
Chairman, JEDEC Board of Directors. “It is intended to meet the power,
bandwidth, packaging, cost and compatibility requirements of the world’s
most advanced mobile systems.” Developed by JEDEC’s JC-42.6 Subcommittee
for Low Power Memories, the JESD209-4 LPDDR4 standard can be downloaded
from the JEDEC website for free by clicking here.
The market for mobile computing continues to grow, and with it the
demand for ever faster devices and ever longer operation on a single
charge. LPDDR4 launches with an I/O data rate of 3200 MT/s and a target
speed of 4266 MT/s, compared to 2133 MT/s for LPDDR3. To achieve this
performance, the members of the committee had to completely redesign the
architecture, going from a one-channel die with 16 bits per channel to a
two-channel die with 16 bits per channel, for a total of 32 bits.
“LPDDR3 was an evolutionary change from LPDDR2. With LPDDR4, the
architecture is completely different,” said Hung Vuong, Chairman of
JC-42.6. “We knew the only way to achieve the performance that the
industry required was to make a total departure from previous
generations.” The two-channel architecture reduces the distance data
signals must travel from the memory array to the I/O bond pads. This
reduces the power required to transmit the large amount of data the
LPDDR4 interface requires. Because most of the area of a memory device
is taken up by the memory array, doubling the interface area has a
minimal impact on the overall footprint.
The two-channel architecture also allows the clock and address bus to be
grouped together with the data bus. Thus, the skew between data bus to
the clock and address bus is minimized, allowing the LPDDR4 device to
reach a higher data rate. This saves power and improves timing margins
compared to the LPDDR3 architecture.
A new approach to signaling
Recognizing that extending the LPDDR3 interface to higher frequencies
would consume too much power, the JEDEC committee decided to implement a
significant change in LPDDR4’s I/O signaling to low-voltage
swing-terminated logic (LVSTL). LPDDR4’s LVSTL I/O signaling voltage of
367 or 440mV is less than 50% the I/O voltage swing of LPDDR3. This
reduces power while enabling high-frequency operation. In addition, by
using Vssq termination and data bus inversion (DBI), termination power
can be minimized since any I/O signal driving a “0” consumes no
Several other steps were taken to save power. The operating voltage was
reduced from the 1.2V of previous generations to 1.1V. Also, the
standard was specifically designed to enable power-efficient operation
at a wide range of frequencies. The I/O can operate in un-terminated
mode at low frequencies with a reduced voltage swing, and the standard
allows rapid switching between operating points so the lower frequency
operation can be used whenever possible.
This rapid switching is enabled by the addition of frequency set points
(FSPs). LPDDR4 specifies two FSPs, which are copies of all the DRAM
registers that store operating parameters which might need to be changed
for operation at two different frequencies. Once both operating
frequencies are trained and the parameters stored in each of the two
corresponding FSPs, switching between the frequencies can be
accomplished by a single mode register write. This reduces the latency
for frequency changes, and enables the system to operate at the optimal
speed for the workload more often.
“It supports end-user flexibility,” noted Vuong. “Some designers like to
run their devices as fast as they can and then put them to sleep. Others
like to run at lower frequencies – and lower power – when possible. A
process might take a little longer but that’s a trade-off they’re
willing to make. We designed LPDDR4 to be flexible enough to allow the
end-user to decide what they want to do.” With that flexibility comes
superior performance – an LPDDR4 device, at a similar data rate, will
consume less power than an LPDDR3 device.
Key specifications include:
Internal Vref supplies for CA and DQ
Data Bus Inversion (DBI-DC)
ODT for CA and DQ
I/O throughput: 3200 MT/s, rising to 4266 MT/s
Signaling voltage: 367mV or 440mV
Operating voltage: 1.1V
Pre-fetch size: 32B per channel
Topology: Point to point, PoP, MCP
Max I/O capacitance: 1.3pF
6-pin SDR CA bus CA training (12 pins per two channels)
As with previous low-power DRAM generations, LPDDR4 does not require a
delay-locked loop (DLL) or phase-locked loop (PLL)
To facilitate understanding and adoption of the LPDDR4 standard, JEDEC
is hosting an LPDDR4 Workshop in Santa Clara, CA on September 23, 2014.
For online registration and agenda information visit: http://www.jedec.org/LPDDR4-ca-2014.
JEDEC is the global leader in the development of standards for the
microelectronics industry. Thousands of volunteers representing nearly
300 member companies work together in 50 JEDEC committees to meet the
needs of every segment of the industry, manufacturers and consumers
alike. The publications and standards generated by JEDEC committees are
accepted throughout the world. All JEDEC standards are available for
free download from the JEDEC website. For more information, visit www.jedec.org.
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